1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit, and more particularly, the present invention relates to an input circuit which converts a voltage level of an external signal and which performs a matching of a logic level.
This application is a counterpart of Japanese application Serial Number 344131/1997, filed Nov. 27, 1997, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing an input circuit according to a conventional semiconductor integrated circuit.
As shown in FIG. 1, the input circuit 101 is made up of a bonding pad BP, a noise absorption portion NP, an inverter IV1 as a voltage level converting circuit, and an inverter IV2. In this circuit, the noise absorption portion NP is made up of a resistor R1, and an N-channel MOS transistor 107, and is used for absorbing electrostatic noise. The inverter IV1 is made up of a P-channel MOS transistor 103 and an N-channel MOS transistor 105. The external signal Sin is inputted from the bonding pad BP, which connected to a drain of the N-channel MOS transistor 107 and to the resistor R1. The N-channel MOS transistor 107 has a gate and a source which are connected to a ground potential GND. The resistor R1 is connected to respective gates of the P-channel MOS transistor 103 and the N-channel MOS transistor 105 via a node N1. The drain of the P-channel MOS transistor 103 is connected to the drain of the N-channel MOS transistor 105 via a node N2. The node N2 is connected to an input terminal of the inverter IV2. The P-channel MOS transistor 103 has a source which is connected to a power supply voltage Vcc. The N-channel MOS transistor 105 has a source which is connected to a ground potential GND. The inverter IV2 has an output terminal which is connected to an internal circuit IS.
FIG. 2 is a diagram for describing an operation of an input circuit according to a conventional semiconductor integrated circuit.
As shown in FIG. 2, in a semiconductor integrated circuit having a supply voltage Vcc of 3.3 V, when assuring LVTTL level as a voltage amplitude, an H level of the eternal signal Sin is defined so as to be more than 2.0 V and an L level of the external signal Sin is defined so as to be less than 0.8 V. When the external signal Sin having a lowest voltage for an H level of 2.0 V is inputted to the bonding pad BP, the external signal Sin is applied to the node N1 via the noise absorption portion NP. Any disturbance surge current within the external signal Sin is removed by the noise absorption portion NP. The voltage 2.0 V applied to the node N1 is applied to the respective gates of the P-channel MOS transistor 103 and the N-channel MOS transistor 105. At this time, the power supply voltage Vcc is defined as 3.3 V, and therefore a gate-source voltage of the P-channel MOS transistor 103 is defined as -1.3 V. As a result, the P-channel MOS transistor 103 turns on. On the other hand, a gate-source voltage of the N-channel MOS transistor 105 is defined as 2.0 V. As a result, the N-channel MOS transistor 105 also turns on. Therefore, both of the P-channel MOS transistor 103 and the N-channel MOS transistor 105 turn on, but absolute value of the gate-source voltage of the N-channel MOS transistor 105 is larger than that of the P-channel MOS transistor 103, as a result the node N2 becomes a potential VL closed to the ground potential. In this time, the potential VL of the node N2 is a sufficient low value compared to a threshold voltage Vth of the inverter IV2, as a result the inverter IV2 outputs an H level signal to the internal circuit IS. Next, the external signal Sin changes from an H level of 2.0 V to an L level of 0.8 V during time t1 to time t2. As a result gate potentials of the P-channel MOS transistor 103 and the N-channel MOS transistor 105 become 0.8 V. Accordingly, the gate-source voltage of the P-channel MOS transistor 103 becomes -2.5 V and the P-channel MOS transistor 103 continuously has turned on. On the other hand, the gate-source voltage of the N-channel MOS transistor 105 becomes 0.8 V and the N-channel MOS transistor 105 continuously has turned on. Therefore, both of the P-channel MOS transistor 103 and the N-channel MOS transistor 105 turn on, but an absolute value of the gate-source voltage of the P-channel MOS transistor 103 is larger than that of the N-channel MOS transistor 105, and as a result the node N2 becomes a potential VH closed to the power supply voltage Vcc. In this time, the potential VH of the node N2 becomes sufficient high value compared to a threshold voltage Vth of the inverter N2, as a result the inverter IV2 outputs an L level signal to the internal circuit IS.